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MAX1112/MAX1113
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________________________________________________________________________________
5
ns
100
tCSS
Figure 1, external clock mode only,
CLOAD = 100pF
ns
CS to SCLK Rise Setup
240
Figure 1, CLOAD = 100pF
ns
20
200
ns
0
tCSH
CONDITIONS
CS to SCLK Rise Hold
240
tDV
CS Fall to Output Enable
Figure 2, CLOAD = 100pF
ns
240
tTR
CS Rise to Output Disable
tSDV
CS Fall to SSTRB Output Enable
(Note 5)
Figure 2, external clock mode only,
CLOAD = 100pF
ns
240
tSTR
CS Rise to SSTRB Output
Disable (Note 5)
Figure 11, internal clock mode only
ns
0
tSCK
SSTRB Rise to SCLK Rise
(Note 5)
ns
200
tCH
SCLK Pulse Width High
ns
200
tCL
SCLK Pulse Width Low
CLOAD = 100pF
ns
240
tSSTRB
SCLK Fall to SSTRB
ns
0
tDH
DIN to SCLK Hold
s
1
tACQ
Track/Hold Acquisition Time
ns
100
tDS
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS (Figures 8 and 9)
(VDD = 4.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
Note 1:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2:
VREFIN = 4.096V, offset nulled.
Note 3:
On-channel grounded; sine wave applied to all off-channels.
Note 4:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:
Guaranteed by design. Not subject to production testing.
Note 6:
Common-mode range for the analog inputs is from AGND to VDD.
Note 7:
External load should not change during the conversion for specified accuracy.
Note 8:
External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9:
Measured as
| VFS (4.5V) - VFS (5.5V) |.
Note 10: 1F at REFOUT; internal reference settling to 0.5 LSB.
ns
tDO
SCLK Fall to Output Data Valid
Figure 1, CLOAD = 100pF
External reference
20
Internal reference (Note 10)
s
24
tWAKE
Wakeup Time
ms
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